summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/cpu/i386/i386.h
diff options
context:
space:
mode:
Diffstat (limited to 'src/devices/cpu/i386/i386.h')
-rw-r--r--src/devices/cpu/i386/i386.h121
1 files changed, 35 insertions, 86 deletions
diff --git a/src/devices/cpu/i386/i386.h b/src/devices/cpu/i386/i386.h
index 4a691f9a1e7..1de76d49339 100644
--- a/src/devices/cpu/i386/i386.h
+++ b/src/devices/cpu/i386/i386.h
@@ -16,7 +16,6 @@
#include "divtlb.h"
#include "i386dasm.h"
-#include "cache.h"
#define INPUT_LINE_A20 1
#define INPUT_LINE_SMI 2
@@ -95,13 +94,6 @@ protected:
virtual u16 mem_pr16(offs_t address) { return macache32->read_word(address); }
virtual u32 mem_pr32(offs_t address) { return macache32->read_dword(address); }
- virtual u8 mem_prd8(offs_t address) { return m_program->read_byte(address); }
- virtual u16 mem_prd16(offs_t address) { return m_program->read_word(address); }
- virtual u32 mem_prd32(offs_t address) { return m_program->read_dword(address); }
- virtual void mem_pwd8(offs_t address, u8 data) { m_program->write_byte(address, data); }
- virtual void mem_pwd16(offs_t address, u16 data) { m_program->write_word(address, data); }
- virtual void mem_pwd32(offs_t address, u32 data) { m_program->write_dword(address, data); }
-
address_space_config m_program_config;
address_space_config m_io_config;
@@ -391,27 +383,32 @@ protected:
void register_state_i386();
void register_state_i386_x87();
void register_state_i386_x87_xmm();
- inline uint32_t i386_translate(int segment, uint32_t ip, int rwn);
+ uint32_t i386_translate(int segment, uint32_t ip, int rwn);
inline vtlb_entry get_permissions(uint32_t pte, int wp);
bool i386_translate_address(int intention, offs_t *address, vtlb_entry *entry);
- inline bool translate_address(int pl, int type, uint32_t *address, uint32_t *error);
- inline void CHANGE_PC(uint32_t pc);
+ bool translate_address(int pl, int type, uint32_t *address, uint32_t *error);
+ void CHANGE_PC(uint32_t pc);
inline void NEAR_BRANCH(int32_t offs);
inline uint8_t FETCH();
inline uint16_t FETCH16();
inline uint32_t FETCH32();
- inline uint8_t READ8(uint32_t ea);
- inline uint16_t READ16(uint32_t ea);
- inline uint32_t READ32(uint32_t ea);
- inline uint64_t READ64(uint32_t ea);
- inline uint8_t READ8PL0(uint32_t ea);
- inline uint16_t READ16PL0(uint32_t ea);
- inline uint32_t READ32PL0(uint32_t ea);
+ inline uint8_t READ8(uint32_t ea) { return READ8PL(ea, m_CPL); }
+ inline uint16_t READ16(uint32_t ea) { return READ16PL(ea, m_CPL); }
+ inline uint32_t READ32(uint32_t ea) { return READ32PL(ea, m_CPL); }
+ inline uint64_t READ64(uint32_t ea) { return READ64PL(ea, m_CPL); }
+ virtual uint8_t READ8PL(uint32_t ea, uint8_t privilege);
+ virtual uint16_t READ16PL(uint32_t ea, uint8_t privilege);
+ virtual uint32_t READ32PL(uint32_t ea, uint8_t privilege);
+ virtual uint64_t READ64PL(uint32_t ea, uint8_t privilege);
inline void WRITE_TEST(uint32_t ea);
- inline void WRITE8(uint32_t ea, uint8_t value);
- inline void WRITE16(uint32_t ea, uint16_t value);
- inline void WRITE32(uint32_t ea, uint32_t value);
- inline void WRITE64(uint32_t ea, uint64_t value);
+ inline void WRITE8(uint32_t ea, uint8_t value) { WRITE8PL(ea, m_CPL, value); }
+ inline void WRITE16(uint32_t ea, uint16_t value) { WRITE16PL(ea, m_CPL, value); }
+ inline void WRITE32(uint32_t ea, uint32_t value) { WRITE32PL(ea, m_CPL, value); }
+ inline void WRITE64(uint32_t ea, uint64_t value) { WRITE64PL(ea, m_CPL, value); }
+ virtual void WRITE8PL(uint32_t ea, uint8_t privilege, uint8_t value);
+ virtual void WRITE16PL(uint32_t ea, uint8_t privilege, uint16_t value);
+ virtual void WRITE32PL(uint32_t ea, uint8_t privilege, uint32_t value);
+ virtual void WRITE64PL(uint32_t ea, uint8_t privilege, uint64_t value);
inline uint8_t OR8(uint8_t dst, uint8_t src);
inline uint16_t OR16(uint16_t dst, uint16_t src);
inline uint32_t OR32(uint32_t dst, uint32_t src);
@@ -445,10 +442,10 @@ protected:
inline void check_ioperm(offs_t port, uint8_t mask);
inline uint8_t READPORT8(offs_t port);
inline void WRITEPORT8(offs_t port, uint8_t value);
- inline uint16_t READPORT16(offs_t port);
- inline void WRITEPORT16(offs_t port, uint16_t value);
- inline uint32_t READPORT32(offs_t port);
- inline void WRITEPORT32(offs_t port, uint32_t value);
+ virtual uint16_t READPORT16(offs_t port);
+ virtual void WRITEPORT16(offs_t port, uint16_t value);
+ virtual uint32_t READPORT32(offs_t port);
+ virtual void WRITEPORT32(offs_t port, uint32_t value);
uint32_t i386_load_protected_mode_segment(I386_SREG *seg, uint64_t *desc );
void i386_load_call_gate(I386_CALL_GATE *gate);
void i386_set_descriptor_accessed(uint16_t selector);
@@ -490,7 +487,7 @@ protected:
void i386_decode_four_byte38f3();
uint8_t read8_debug(uint32_t ea, uint8_t *data);
uint32_t i386_get_debug_desc(I386_SREG *seg);
- inline void CYCLES(int x);
+ void CYCLES(int x);
inline void CYCLES_RM(int modrm, int r, int m);
uint8_t i386_shift_rotate8(uint8_t modrm, uint32_t value, uint8_t shift);
void i386_adc_rm8_r8();
@@ -1524,6 +1521,17 @@ protected:
virtual u8 mem_pr8(offs_t address) override { return macache16->read_byte(address); };
virtual u16 mem_pr16(offs_t address) override { return macache16->read_word(address); };
virtual u32 mem_pr32(offs_t address) override { return macache16->read_dword(address); };
+
+ virtual uint16_t READ16PL(uint32_t ea, uint8_t privilege) override;
+ virtual uint32_t READ32PL(uint32_t ea, uint8_t privilege) override;
+ virtual uint64_t READ64PL(uint32_t ea, uint8_t privilege) override;
+ virtual void WRITE16PL(uint32_t ea, uint8_t privilege, uint16_t value) override;
+ virtual void WRITE32PL(uint32_t ea, uint8_t privilege, uint32_t value) override;
+ virtual void WRITE64PL(uint32_t ea, uint8_t privilege, uint64_t value) override;
+ virtual uint16_t READPORT16(offs_t port) override;
+ virtual void WRITEPORT16(offs_t port, uint16_t value) override;
+ virtual uint32_t READPORT32(offs_t port) override;
+ virtual void WRITEPORT32(offs_t port, uint32_t value) override;
};
class i486_device : public i386_device
@@ -1632,64 +1640,6 @@ protected:
};
-class athlonxp_device : public pentium_device
-{
-public:
- // construction/destruction
- athlonxp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
-
-protected:
- virtual void opcode_cpuid() override;
- virtual uint64_t opcode_rdmsr(bool &valid_msr) override;
- virtual void opcode_wrmsr(uint64_t data, bool &valid_msr) override;
- virtual void cache_writeback() override;
- virtual void cache_invalidate() override;
- virtual void cache_clean() override;
- virtual void device_start() override;
- virtual void device_reset() override;
- virtual void enter_smm() override;
- virtual void leave_smm() override;
-
- virtual u8 mem_pr8(offs_t address) override { return opcode_read_cache<u8, NATIVE_ENDIAN_VALUE_LE_BE(0, 3)>(address); }
- virtual u16 mem_pr16(offs_t address) override { return opcode_read_cache<u16, NATIVE_ENDIAN_VALUE_LE_BE(0, 2)>(address); }
- virtual u32 mem_pr32(offs_t address) override { return opcode_read_cache<u32, 0>(address); }
- virtual u8 mem_prd8(offs_t address) override { return program_read_cache<u8, NATIVE_ENDIAN_VALUE_LE_BE(0, 3)>(address); }
- virtual u16 mem_prd16(offs_t address) override { return program_read_cache<u16, NATIVE_ENDIAN_VALUE_LE_BE(0, 2)>(address); }
- virtual u32 mem_prd32(offs_t address) override { return program_read_cache<u32, 0>(address); }
- virtual void mem_pwd8(offs_t address, u8 data) override { program_write_cache<u8, NATIVE_ENDIAN_VALUE_LE_BE(0, 3)>(address, data); }
- virtual void mem_pwd16(offs_t address, u16 data) override { program_write_cache<u16, NATIVE_ENDIAN_VALUE_LE_BE(0, 2)>(address, data); }
- virtual void mem_pwd32(offs_t address, u32 data) override { program_write_cache<u32, 0>(address, data); }
-
- // device_memory_interface override
- virtual space_config_vector memory_space_config() const override;
-
-private:
- void parse_mtrrfix(u64 mtrr, offs_t base, int kblock);
- inline int check_cacheable(offs_t address);
- template <int wr> int address_mode(offs_t address);
-
- template <class dt, offs_t xorle> dt opcode_read_cache(offs_t address);
- template <class dt, offs_t xorle> dt program_read_cache(offs_t address);
- template <class dt, offs_t xorle> void program_write_cache(offs_t address, dt data);
-
- DECLARE_READ32_MEMBER(debug_read_memory);
-
- address_space_config m_data_config;
- address_space *m_data;
- address_space_config m_opcodes_config;
- address_space *m_opcodes;
- memory_access_cache<2, 0, ENDIANNESS_LITTLE> *mmacache32;
- uint8_t m_processor_name_string[48];
- offs_t m_msr_top_mem;
- uint64_t m_msr_sys_cfg;
- offs_t m_msr_smm_base;
- uint64_t m_msr_smm_mask;
- uint64_t m_msr_mtrrfix[11];
- uint8_t m_memory_ranges_1m[1024 / 4];
- cpucache<17, 9, Cache2Way, CacheLineBytes64> cache; // 512 sets, 2 ways (cachelines per set), 64 bytes per cacheline
-};
-
-
class pentium4_device : public pentium_device
{
public:
@@ -1714,7 +1664,6 @@ DECLARE_DEVICE_TYPE(MEDIAGX, mediagx_device)
DECLARE_DEVICE_TYPE(PENTIUM_PRO, pentium_pro_device)
DECLARE_DEVICE_TYPE(PENTIUM2, pentium2_device)
DECLARE_DEVICE_TYPE(PENTIUM3, pentium3_device)
-DECLARE_DEVICE_TYPE(ATHLONXP, athlonxp_device)
DECLARE_DEVICE_TYPE(PENTIUM4, pentium4_device)
#endif // MAME_CPU_I386_I386_H