diff options
Diffstat (limited to 'src/devices/cpu/i386/cycles.h')
-rw-r--r-- | src/devices/cpu/i386/cycles.h | 333 |
1 files changed, 0 insertions, 333 deletions
diff --git a/src/devices/cpu/i386/cycles.h b/src/devices/cpu/i386/cycles.h index b6399706858..2ca28aff180 100644 --- a/src/devices/cpu/i386/cycles.h +++ b/src/devices/cpu/i386/cycles.h @@ -6,339 +6,6 @@ #ifndef __CYCLES_H__ #define __CYCLES_H__ -enum X86_CYCLES -{ - CYCLES_MOV_REG_REG, - CYCLES_MOV_REG_MEM, - CYCLES_MOV_MEM_REG, - CYCLES_MOV_IMM_REG, - CYCLES_MOV_IMM_MEM, - CYCLES_MOV_ACC_MEM, - CYCLES_MOV_MEM_ACC, - CYCLES_MOV_REG_SREG, - CYCLES_MOV_MEM_SREG, - CYCLES_MOV_SREG_REG, - CYCLES_MOV_SREG_MEM, - CYCLES_MOVSX_REG_REG, - CYCLES_MOVSX_MEM_REG, - CYCLES_MOVZX_REG_REG, - CYCLES_MOVZX_MEM_REG, - CYCLES_PUSH_RM, - CYCLES_PUSH_REG_SHORT, - CYCLES_PUSH_SREG, - CYCLES_PUSH_IMM, - CYCLES_PUSHA, - CYCLES_POP_RM, - CYCLES_POP_REG_SHORT, - CYCLES_POP_SREG, - CYCLES_POPA, - CYCLES_XCHG_REG_REG, - CYCLES_XCHG_REG_MEM, - CYCLES_IN, - CYCLES_IN_VAR, - CYCLES_OUT, - CYCLES_OUT_VAR, - CYCLES_LEA, - CYCLES_LDS, - CYCLES_LES, - CYCLES_LFS, - CYCLES_LGS, - CYCLES_LSS, - CYCLES_CLC, - CYCLES_CLD, - CYCLES_CLI, - CYCLES_CLTS, - CYCLES_CMC, - CYCLES_LAHF, - CYCLES_POPF, - CYCLES_PUSHF, - CYCLES_SAHF, - CYCLES_STC, - CYCLES_STD, - CYCLES_STI, - CYCLES_ALU_REG_REG, - CYCLES_ALU_REG_MEM, - CYCLES_ALU_MEM_REG, - CYCLES_ALU_IMM_REG, - CYCLES_ALU_IMM_MEM, - CYCLES_ALU_IMM_ACC, - CYCLES_INC_REG, - CYCLES_INC_MEM, - CYCLES_DEC_REG, - CYCLES_DEC_MEM, - CYCLES_CMP_REG_REG, - CYCLES_CMP_REG_MEM, - CYCLES_CMP_MEM_REG, - CYCLES_CMP_IMM_REG, - CYCLES_CMP_IMM_MEM, - CYCLES_CMP_IMM_ACC, - CYCLES_TEST_REG_REG, - CYCLES_TEST_REG_MEM, - CYCLES_TEST_IMM_REG, - CYCLES_TEST_IMM_MEM, - CYCLES_TEST_IMM_ACC, - CYCLES_NEG_REG, - CYCLES_NEG_MEM, - CYCLES_AAA, - CYCLES_AAS, - CYCLES_DAA, - CYCLES_DAS, - CYCLES_MUL8_ACC_REG, - CYCLES_MUL8_ACC_MEM, - CYCLES_MUL16_ACC_REG, - CYCLES_MUL16_ACC_MEM, - CYCLES_MUL32_ACC_REG, - CYCLES_MUL32_ACC_MEM, - CYCLES_IMUL8_ACC_REG, - CYCLES_IMUL8_ACC_MEM, - CYCLES_IMUL16_ACC_REG, - CYCLES_IMUL16_ACC_MEM, - CYCLES_IMUL32_ACC_REG, - CYCLES_IMUL32_ACC_MEM, - CYCLES_IMUL8_REG_REG, - CYCLES_IMUL8_REG_MEM, - CYCLES_IMUL16_REG_REG, - CYCLES_IMUL16_REG_MEM, - CYCLES_IMUL32_REG_REG, - CYCLES_IMUL32_REG_MEM, - CYCLES_IMUL16_REG_IMM_REG, - CYCLES_IMUL16_MEM_IMM_REG, - CYCLES_IMUL32_REG_IMM_REG, - CYCLES_IMUL32_MEM_IMM_REG, - CYCLES_DIV8_ACC_REG, - CYCLES_DIV8_ACC_MEM, - CYCLES_DIV16_ACC_REG, - CYCLES_DIV16_ACC_MEM, - CYCLES_DIV32_ACC_REG, - CYCLES_DIV32_ACC_MEM, - CYCLES_IDIV8_ACC_REG, - CYCLES_IDIV8_ACC_MEM, - CYCLES_IDIV16_ACC_REG, - CYCLES_IDIV16_ACC_MEM, - CYCLES_IDIV32_ACC_REG, - CYCLES_IDIV32_ACC_MEM, - CYCLES_AAD, - CYCLES_AAM, - CYCLES_CBW, - CYCLES_CWD, - CYCLES_ROTATE_REG, - CYCLES_ROTATE_MEM, - CYCLES_ROTATE_CARRY_REG, - CYCLES_ROTATE_CARRY_MEM, - CYCLES_SHLD_REG, - CYCLES_SHLD_MEM, - CYCLES_SHRD_REG, - CYCLES_SHRD_MEM, - CYCLES_NOT_REG, - CYCLES_NOT_MEM, - CYCLES_CMPS, - CYCLES_INS, - CYCLES_LODS, - CYCLES_MOVS, - CYCLES_OUTS, - CYCLES_SCAS, - CYCLES_STOS, - CYCLES_XLAT, - CYCLES_REP_CMPS_BASE, - CYCLES_REP_INS_BASE, - CYCLES_REP_LODS_BASE, - CYCLES_REP_MOVS_BASE, - CYCLES_REP_OUTS_BASE, - CYCLES_REP_SCAS_BASE, - CYCLES_REP_STOS_BASE, - CYCLES_REP_CMPS, - CYCLES_REP_INS, - CYCLES_REP_LODS, - CYCLES_REP_MOVS, - CYCLES_REP_OUTS, - CYCLES_REP_SCAS, - CYCLES_REP_STOS, - CYCLES_BSF_BASE, - CYCLES_BSF, - CYCLES_BSR_BASE, - CYCLES_BSR, - CYCLES_BT_IMM_REG, - CYCLES_BT_IMM_MEM, - CYCLES_BT_REG_REG, - CYCLES_BT_REG_MEM, - CYCLES_BTC_IMM_REG, - CYCLES_BTC_IMM_MEM, - CYCLES_BTC_REG_REG, - CYCLES_BTC_REG_MEM, - CYCLES_BTR_IMM_REG, - CYCLES_BTR_IMM_MEM, - CYCLES_BTR_REG_REG, - CYCLES_BTR_REG_MEM, - CYCLES_BTS_IMM_REG, - CYCLES_BTS_IMM_MEM, - CYCLES_BTS_REG_REG, - CYCLES_BTS_REG_MEM, - CYCLES_CALL, // E8 - CYCLES_CALL_REG, // FF /2 - CYCLES_CALL_MEM, // FF /2 - CYCLES_CALL_INTERSEG, // 9A - CYCLES_CALL_REG_INTERSEG, // FF /3 - CYCLES_CALL_MEM_INTERSEG, // FF /3 - CYCLES_JMP_SHORT, // EB - CYCLES_JMP, // E9 - CYCLES_JMP_REG, // FF /4 - CYCLES_JMP_MEM, // FF /4 - CYCLES_JMP_INTERSEG, // EA - CYCLES_JMP_REG_INTERSEG, // FF /5 - CYCLES_JMP_MEM_INTERSEG, // FF /5 - CYCLES_RET, // C3 - CYCLES_RET_IMM, // C2 - CYCLES_RET_INTERSEG, // CB - CYCLES_RET_IMM_INTERSEG, // CA - CYCLES_JCC_DISP8, - CYCLES_JCC_FULL_DISP, - CYCLES_JCC_DISP8_NOBRANCH, - CYCLES_JCC_FULL_DISP_NOBRANCH, - CYCLES_JCXZ, - CYCLES_JCXZ_NOBRANCH, - CYCLES_LOOP, - CYCLES_LOOPZ, - CYCLES_LOOPNZ, - CYCLES_SETCC_REG, - CYCLES_SETCC_MEM, - CYCLES_ENTER, - CYCLES_LEAVE, - CYCLES_INT, - CYCLES_INT3, - CYCLES_INTO_OF1, - CYCLES_INTO_OF0, - CYCLES_BOUND_IN_RANGE, - CYCLES_BOUND_OUT_RANGE, - CYCLES_IRET, - CYCLES_HLT, - CYCLES_MOV_REG_CR0, - CYCLES_MOV_REG_CR2, - CYCLES_MOV_REG_CR3, - CYCLES_MOV_CR_REG, - CYCLES_MOV_REG_DR0_3, - CYCLES_MOV_REG_DR6_7, - CYCLES_MOV_DR6_7_REG, - CYCLES_MOV_DR0_3_REG, - CYCLES_MOV_REG_TR6_7, - CYCLES_MOV_TR6_7_REG, - CYCLES_NOP, - CYCLES_WAIT, - CYCLES_ARPL_REG, - CYCLES_ARPL_MEM, - CYCLES_LAR_REG, - CYCLES_LAR_MEM, - CYCLES_LGDT, - CYCLES_LIDT, - CYCLES_LLDT_REG, - CYCLES_LLDT_MEM, - CYCLES_LMSW_REG, - CYCLES_LMSW_MEM, - CYCLES_LSL_REG, - CYCLES_LSL_MEM, - CYCLES_LTR_REG, - CYCLES_LTR_MEM, - CYCLES_SGDT, - CYCLES_SIDT, - CYCLES_SLDT_REG, - CYCLES_SLDT_MEM, - CYCLES_SMSW_REG, - CYCLES_SMSW_MEM, - CYCLES_STR_REG, - CYCLES_STR_MEM, - CYCLES_VERR_REG, - CYCLES_VERR_MEM, - CYCLES_VERW_REG, - CYCLES_VERW_MEM, - CYCLES_LOCK, - - CYCLES_BSWAP, - CYCLES_CMPXCHG8B, - CYCLES_CMPXCHG, - CYCLES_CPUID, - CYCLES_CPUID_EAX1, - CYCLES_INVD, - CYCLES_XADD, - CYCLES_RDTSC, - CYCLES_RSM, - CYCLES_RDMSR, - - CYCLES_FABS, - CYCLES_FADD, - CYCLES_FBLD, - CYCLES_FBSTP, - CYCLES_FCHS, - CYCLES_FCLEX, - CYCLES_FCOM, - CYCLES_FCOS, - CYCLES_FDECSTP, - CYCLES_FDISI, - CYCLES_FDIV, - CYCLES_FDIVR, - CYCLES_FENI, - CYCLES_FFREE, - CYCLES_FIADD, - CYCLES_FICOM, - CYCLES_FIDIV, - CYCLES_FILD, - CYCLES_FIMUL, - CYCLES_FINCSTP, - CYCLES_FINIT, - CYCLES_FIST, - CYCLES_FISUB, - CYCLES_FLD, - CYCLES_FLDZ, - CYCLES_FLD1, - CYCLES_FLDL2E, - CYCLES_FLDL2T, - CYCLES_FLDLG2, - CYCLES_FLDLN2, - CYCLES_FLDPI, - CYCLES_FLDCW, - CYCLES_FLDENV, - CYCLES_FMUL, - CYCLES_FNOP, - CYCLES_FPATAN, - CYCLES_FPREM, - CYCLES_FPREM1, - CYCLES_FPTAN, - CYCLES_FRNDINT, - CYCLES_FRSTOR, - CYCLES_FSAVE, - CYCLES_FSCALE, - CYCLES_FSETPM, - CYCLES_FSIN, - CYCLES_FSINCOS, - CYCLES_FSQRT, - CYCLES_FST, - CYCLES_FSTCW, - CYCLES_FSTENV, - CYCLES_FSTSW, - CYCLES_FSUB, - CYCLES_FSUBR, - CYCLES_FTST, - CYCLES_FUCOM, - CYCLES_FXAM, - CYCLES_FXCH, - CYCLES_FXTRACT, - CYCLES_FYL2X, - CYCLES_FYL2XPI, - CYCLES_CMPXCHG_REG_REG_T, - CYCLES_CMPXCHG_REG_REG_F, - CYCLES_CMPXCHG_REG_MEM_T, - CYCLES_CMPXCHG_REG_MEM_F, - CYCLES_XADD_REG_REG, - CYCLES_XADD_REG_MEM, - - CYCLES_NUM_OPCODES -}; - - -#define CPU_CYCLES_I386 0 -#define CPU_CYCLES_I486 1 -#define CPU_CYCLES_PENTIUM 2 -#define CPU_CYCLES_MEDIAGX 3 - - struct X86_CYCLE_TABLE { X86_CYCLES op; |