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Diffstat (limited to 'src/devices/bus/snes/sa1.cpp')
-rw-r--r--src/devices/bus/snes/sa1.cpp192
1 files changed, 100 insertions, 92 deletions
diff --git a/src/devices/bus/snes/sa1.cpp b/src/devices/bus/snes/sa1.cpp
index e81bb5e2d1a..b25a06d5255 100644
--- a/src/devices/bus/snes/sa1.cpp
+++ b/src/devices/bus/snes/sa1.cpp
@@ -253,6 +253,7 @@ void sns_sa1_device::recalc_irqs()
// handle this separately to avoid accessing recursively the regs?
+template <bool SA1Read>
uint8_t sns_sa1_device::var_length_read(uint32_t offset)
{
// handle 0xffea/0xffeb/0xffee/0xffef
@@ -274,10 +275,10 @@ uint8_t sns_sa1_device::var_length_read(uint32_t offset)
return read_h(offset & 0x7fffff);
if ((offset & 0x40e000) == 0x006000) //$00-3f|80-bf:6000-7fff
- return read_bwram((m_bwram_snes * 0x2000) + (offset & 0x1fff));
+ return read_bwram<SA1Read>((m_bwram_snes * 0x2000) + (offset & 0x1fff));
if ((offset & 0xf00000) == 0x400000) //$40-4f:0000-ffff
- return read_bwram(offset & 0xfffff);
+ return read_bwram<SA1Read>(offset & 0xfffff);
if ((offset & 0x40f800) == 0x000000) //$00-3f|80-bf:0000-07ff
return read_iram(offset);
@@ -324,11 +325,11 @@ void sns_sa1_device::dma_transfer()
case 1: // BWRAM
if ((dma_src & 0x40e000) == 0x006000)
{
- data = read_bwram((m_bwram_sa1 * 0x2000) + (dma_src & 0x1fff));
+ data = read_bwram<true>((m_bwram_sa1 * 0x2000) + (dma_src & 0x1fff));
}
if ((dma_src & 0xf00000) == 0x400000)
{
- data = read_bwram(dma_src & 0xfffff);
+ data = read_bwram<true>(dma_src & 0xfffff);
}
break;
@@ -362,70 +363,7 @@ void sns_sa1_device::dma_transfer()
void sns_sa1_device::dma_cctype1_transfer()
{
- while (m_dma_cnt--)
- {
- uint8_t data = 0; // open bus?
- uint32_t dma_src = m_src_addr++;
- uint32_t dma_dst = m_dst_addr++;
-
- // source and destination cannot be the same
- // source = { 0=ROM, 1=BWRAM, 2=IRAM }
- // destination = { 0=IRAM, 1=BWRAM }
- if ((m_dma_ctrl & 0x03) == 1 && (m_dma_ctrl & 0x04) == 0x04) continue;
- if ((m_dma_ctrl & 0x03) == 2 && (m_dma_ctrl & 0x04) == 0x00) continue;
-
- switch (m_dma_ctrl & 0x03)
- {
- case 0: // ROM
- if ((dma_src & 0x408000) == 0x008000 && (dma_src & 0x800000) == 0x000000)
- {
- data = read_l(dma_src & 0x7fffff);
- }
- if ((dma_src & 0x408000) == 0x008000 && (dma_src & 0x800000) == 0x800000)
- {
- data = read_h(dma_src & 0x7fffff);
- }
- if ((dma_src & 0xc00000) == 0xc00000)
- {
- data = read_h(dma_src & 0x7fffff);
- }
- break;
-
- case 1: // BWRAM
- if ((dma_src & 0x40e000) == 0x006000)
- {
- data = read_bwram((m_bwram_sa1 * 0x2000) + (dma_src & 0x1fff));
- }
- if ((dma_src & 0xf00000) == 0x400000)
- {
- data = read_bwram(dma_src & 0xfffff);
- }
- break;
-
- case 2: // IRAM
- data = read_iram(dma_src);
- break;
- }
-
- switch (m_dma_ctrl & 0x04)
- {
- case 0x00: // IRAM
- write_iram(dma_dst, data);
- break;
-
- case 0x04: // BWRAM
- if ((dma_dst & 0x40e000) == 0x006000)
- {
- write_bwram((m_bwram_sa1 * 0x2000) + (dma_dst & 0x1fff), data);
- }
- if ((dma_dst & 0xf00000) == 0x400000)
- {
- write_bwram(dma_dst & 0xfffff, data);
- }
- break;
- }
- }
-
+ m_cconv1_dma_active = true;
m_scpu_flags |= SCPU_IRQ_CHARCONV;
recalc_irqs();
}
@@ -434,6 +372,7 @@ void sns_sa1_device::dma_cctype2_transfer()
{
}
+template<bool SA1Read>
uint8_t sns_sa1_device::read_regs(uint32_t offset)
{
uint8_t value = 0xff;
@@ -496,8 +435,7 @@ uint8_t sns_sa1_device::read_regs(uint32_t offset)
case 0x10c:
// Var-Length Read Port Low
{
- uint32_t data = (var_length_read(m_vda + 0) << 0) | (var_length_read(m_vda + 1) << 8)
- | (var_length_read(m_vda + 2) << 16);
+ uint32_t data = (var_length_read<SA1Read>(m_vda + 0) << 0) | (var_length_read<SA1Read>(m_vda + 1) << 8) | (var_length_read<SA1Read>(m_vda + 2) << 16);
data >>= m_vbit;
value = (data >> 0) & 0xff;
}
@@ -505,8 +443,7 @@ uint8_t sns_sa1_device::read_regs(uint32_t offset)
case 0x10d:
// Var-Length Read Port High
{
- uint32_t data = (var_length_read(m_vda + 0) << 0) | (var_length_read(m_vda + 1) << 8)
- | (var_length_read(m_vda + 2) << 16);
+ uint32_t data = (var_length_read<SA1Read>(m_vda + 0) << 0) | (var_length_read<SA1Read>(m_vda + 1) << 8) | (var_length_read<SA1Read>(m_vda + 2) << 16);
data >>= m_vbit;
if (m_drm == 1)
@@ -758,6 +695,13 @@ void sns_sa1_device::write_regs(uint32_t offset, uint8_t data)
case 0x031:
// Both CDMA 00h Character Conversion DMA Parameters (W)
m_dma_ccparam = data;
+ m_dma_cconv_size = (data >> 2) & 7;
+ if (m_dma_cconv_size > 5) m_dma_cconv_size = 5;
+ m_dma_cconv_bits = data & 3;
+ if (m_dma_cconv_bits > 2) m_dma_cconv_bits = 2;
+
+ if (BIT(data, 7))
+ m_cconv1_dma_active = false;
break;
case 0x032:
// DMA Source Device Start Address Low
@@ -793,7 +737,7 @@ void sns_sa1_device::write_regs(uint32_t offset, uint8_t data)
break;
case 0x037:
// DMA Dest Device Start Address High
- m_dst_addr = (m_dst_addr & 0xffff00) | (data << 16);
+ m_dst_addr = (m_dst_addr & 0x00ffff) | (data << 16);
if (m_dma_ctrl & 0x80)
{
if (!(m_dma_ctrl & 0x20) && m_dma_ctrl & 0x04) // Normal DMA to BWRAM
@@ -937,6 +881,65 @@ void sns_sa1_device::write_iram(uint32_t offset, uint8_t data)
m_internal_ram[offset & 0x7ff] = data;
}
+uint8_t sns_sa1_device::read_cconv1_dma(uint32_t offset)
+{
+ uint32_t store_mask = (1 << (6 - m_dma_cconv_bits)) - 1;
+
+ if ((offset & store_mask) == 0)
+ {
+ uint32_t bpp = 2 << (2 - m_dma_cconv_bits);
+ uint32_t tile_stride = (8 << m_dma_cconv_size) >> m_dma_cconv_bits;
+ uint32_t bwram_addr_mask = m_nvram.size() - 1;
+ uint32_t tile = ((offset - m_src_addr) & bwram_addr_mask) >> (6 - m_dma_cconv_bits);
+ uint32_t ty = (tile >> m_dma_cconv_size);
+ uint32_t tx = tile & ((1 << m_dma_cconv_size) - 1);
+ uint32_t bwram_src = m_src_addr + ty * 8 * tile_stride + tx * bpp;
+
+ for (uint32_t y = 0; y < 8; y++)
+ {
+ uint64_t raw_pixels = 0;
+ for (uint64_t bit = 0; bit < bpp; bit++)
+ {
+ raw_pixels |= (uint64_t)m_nvram[(bwram_src + bit) & bwram_addr_mask] << (bit << 3);
+ }
+ bwram_src += tile_stride;
+
+ uint8_t linear[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+ for (uint32_t x = 0; x < 8; x++)
+ {
+ linear[0] |= BIT(raw_pixels, 0) << (7 - x);
+ linear[1] |= BIT(raw_pixels, 1) << (7 - x);
+ if (m_dma_cconv_bits == 2)
+ {
+ raw_pixels >>= 2;
+ continue;
+ }
+ linear[2] |= BIT(raw_pixels, 2) << (7 - x);
+ linear[3] |= BIT(raw_pixels, 3) << (7 - x);
+ if (m_dma_cconv_bits == 1)
+ {
+ raw_pixels >>= 4;
+ continue;
+ }
+ linear[4] |= BIT(raw_pixels, 4) << (7 - x);
+ linear[5] |= BIT(raw_pixels, 5) << (7 - x);
+ linear[6] |= BIT(raw_pixels, 6) << (7 - x);
+ linear[7] |= BIT(raw_pixels, 7) << (7 - x);
+ raw_pixels >>= 8;
+ }
+
+ for (uint32_t byte = 0; byte < bpp; byte++)
+ {
+ uint32_t dst_addr = m_dst_addr + (y << 1) + ((byte & 6) << 3) + (byte & 1);
+ write_iram(dst_addr, linear[byte]);
+ }
+ }
+ }
+
+ return read_iram(m_dst_addr + (offset & store_mask));
+}
+
+template<bool SA1Read>
uint8_t sns_sa1_device::read_bwram(uint32_t offset)
{
int shift;
@@ -945,6 +948,11 @@ uint8_t sns_sa1_device::read_bwram(uint32_t offset)
if (m_nvram.empty())
return 0xff; // this should probably never happen, or are there SA-1 games with no BWRAM?
+ if (m_cconv1_dma_active && !SA1Read)
+ {
+ return read_cconv1_dma(offset);
+ }
+
if (offset < 0x100000)
return m_nvram[offset & (m_nvram.size() - 1)];
@@ -954,16 +962,16 @@ uint8_t sns_sa1_device::read_bwram(uint32_t offset)
if (m_bwram_sa1_format)
{
// 2bits mode
- offset /= 4;
- shift = ((offset % 4) * 2);
+ shift = ((offset & 3) << 1);
mask = 0x03;
+ offset >>= 2;
}
else
{
// 4bits mode
- offset /= 2;
- shift = ((offset % 2) * 4);
+ shift = ((offset & 1) << 2);
mask = 0x0f;
+ offset >>= 1;
}
// only return the correct bits
@@ -989,16 +997,16 @@ void sns_sa1_device::write_bwram(uint32_t offset, uint8_t data)
if (m_bwram_sa1_format)
{
// 2bits mode
- offset /= 4;
- data = (data & 0x03) << ((offset % 4) * 2);
- mask = 0x03 << ((offset % 4) * 2);
+ data = (data & 0x03) << ((offset & 3) << 1);
+ mask = 0x03 << ((offset & 3) << 1);
+ offset >>= 2;
}
else
{
// 4bits mode
- offset /= 2;
- data = (data & 0x0f) << ((offset % 2) * 4);
- mask = 0x0f << ((offset % 2) * 4);
+ data = (data & 0x0f) << ((offset & 1) << 2);
+ mask = 0x0f << ((offset & 1) << 2);
+ offset >>= 1;
}
// only change the correct bits, keeping the rest untouched
@@ -1096,16 +1104,16 @@ uint8_t sns_sa1_device::chip_read(offs_t offset)
uint16_t address = offset & 0xffff;
if (offset < 0x400000 && address >= 0x2200 && address < 0x2400)
- return read_regs(address & 0x1ff); // SA-1 Regs
+ return read_regs<false>(address & 0x1ff); // SA-1 Regs
if (offset < 0x400000 && address >= 0x3000 && address < 0x3800)
return read_iram(address & 0x7ff); // Internal SA-1 RAM (2K)
if (offset < 0x400000 && address >= 0x6000 && address < 0x8000)
- return read_bwram((m_bwram_snes * 0x2000) + (offset & 0x1fff)); // SA-1 BWRAM
+ return read_bwram<false>((m_bwram_snes * 0x2000) + (offset & 0x1fff)); // SA-1 BWRAM
if (offset >= 0x400000 && offset < 0x500000)
- return read_bwram(offset & 0xfffff); // SA-1 BWRAM again (but not called for the [c0-cf] range, because it's not mirrored)
+ return read_bwram<false>(offset & 0xfffff); // SA-1 BWRAM again (but not called for the [c0-cf] range, because it's not mirrored)
return 0xff;
}
@@ -1148,12 +1156,12 @@ uint8_t sns_sa1_device::sa1_hi_r(offs_t offset)
if (address < 0x0800)
return read_iram(offset); // Internal SA-1 RAM (2K)
else if (address >= 0x2200 && address < 0x2400)
- return read_regs(offset & 0x1ff); // SA-1 Regs
+ return read_regs<true>(offset & 0x1ff); // SA-1 Regs
else if (address >= 0x3000 && address < 0x3800)
return read_iram(offset); // Internal SA-1 RAM (2K)
}
else if (address < 0x8000)
- return read_bwram((m_bwram_sa1 * 0x2000) + (offset & 0x1fff) + (m_bwram_sa1_source * 0x100000)); // SA-1 BWRAM
+ return read_bwram<true>((m_bwram_sa1 * 0x2000) + (offset & 0x1fff) + (m_bwram_sa1_source * 0x100000)); // SA-1 BWRAM
else
return read_h(offset); // ROM
@@ -1174,12 +1182,12 @@ uint8_t sns_sa1_device::sa1_lo_r(offs_t offset)
if (address < 0x0800)
return read_iram(offset); // Internal SA-1 RAM (2K)
else if (address >= 0x2200 && address < 0x2400)
- return read_regs(offset & 0x1ff); // SA-1 Regs
+ return read_regs<true>(offset & 0x1ff); // SA-1 Regs
else if (address >= 0x3000 && address < 0x3800)
return read_iram(offset); // Internal SA-1 RAM (2K)
}
else if (address < 0x8000)
- return read_bwram((m_bwram_sa1 * 0x2000) + (offset & 0x1fff) + (m_bwram_sa1_source * 0x100000)); // SA-1 BWRAM
+ return read_bwram<true>((m_bwram_sa1 * 0x2000) + (offset & 0x1fff) + (m_bwram_sa1_source * 0x100000)); // SA-1 BWRAM
else if (offset == 0xffee)
{
return m_sa1_irq & 0xff;
@@ -1210,9 +1218,9 @@ uint8_t sns_sa1_device::sa1_lo_r(offs_t offset)
return 0xff; // maybe open bus? same as the main system one or diff? (currently not accessible from carts anyway...)
}
else if (offset < 0x500000)
- return read_bwram(offset & 0xfffff); // SA-1 BWRAM (not mirrored above!)
+ return read_bwram<true>(offset & 0xfffff); // SA-1 BWRAM (not mirrored above!)
else if (offset >= 0x600000 && offset < 0x700000)
- return read_bwram((offset & 0xfffff) + 0x100000); // SA-1 BWRAM Bitmap mode
+ return read_bwram<true>((offset & 0xfffff) + 0x100000); // SA-1 BWRAM Bitmap mode
else
return 0xff; // nothing should be mapped here, so maybe open bus?
}