diff options
author | hap <happppp@users.noreply.github.com> | 2015-02-07 22:04:02 +0100 |
---|---|---|
committer | hap <happppp@users.noreply.github.com> | 2015-02-07 22:04:02 +0100 |
commit | c34536b28545ef289ead05c9c1c33744f323e55c (patch) | |
tree | 95055682c051d55224036bbbf767050106d0e6e7 | |
parent | 2756a23b1a37c5f7d5f9b7b834e80af0ac6cccab (diff) |
ucom4 skeleton opcode handlers
-rw-r--r-- | src/emu/cpu/amis2000/amis2000.c | 5 | ||||
-rw-r--r-- | src/emu/cpu/amis2000/amis2000op.inc | 8 | ||||
-rw-r--r-- | src/emu/cpu/ucom4/ucom4.c | 168 | ||||
-rw-r--r-- | src/emu/cpu/ucom4/ucom4.h | 100 | ||||
-rw-r--r-- | src/emu/cpu/ucom4/ucom4op.inc | 580 |
5 files changed, 834 insertions, 27 deletions
diff --git a/src/emu/cpu/amis2000/amis2000.c b/src/emu/cpu/amis2000/amis2000.c index bc961077595..a49d86e5489 100644 --- a/src/emu/cpu/amis2000/amis2000.c +++ b/src/emu/cpu/amis2000/amis2000.c @@ -306,10 +306,11 @@ void amis2000_device::execute_run() case 0x48: op_lbe(); break; case 0x4c: op_lbep(); break; } - break; + break; // 0xfc } - break; + break; // 0xff + } // big switch } } diff --git a/src/emu/cpu/amis2000/amis2000op.inc b/src/emu/cpu/amis2000/amis2000op.inc index ed6f6158d89..e8b0f233727 100644 --- a/src/emu/cpu/amis2000/amis2000op.inc +++ b/src/emu/cpu/amis2000/amis2000op.inc @@ -388,13 +388,13 @@ void amis2000_device::op_szk() void amis2000_device::op_sbe() { - // SBE: skip next on BL equ E + // SBE: skip next on BL equals E m_skip = (m_bl == m_e); } void amis2000_device::op_sam() { - // SAM: skip next on ACC equ RAM + // SAM: skip next on ACC equals RAM m_skip = (m_acc == ram_r()); } @@ -421,7 +421,7 @@ void amis2000_device::op_tf2() void amis2000_device::op_adcs() { - // ADCS: add RAM to ACC+carry, skip next on no carry + // ADCS: add RAM to ACC+carry, skip next on not carry m_acc += ram_r() + m_carry; m_carry = m_acc >> 4 & 1; m_skip = !m_carry; @@ -430,7 +430,7 @@ void amis2000_device::op_adcs() void amis2000_device::op_adis() { - // ADIS X: add X to ACC, skip next on no carry + // ADIS X: add X to ACC, skip next on not carry UINT8 param = m_op & 0x0f; m_acc += param; m_skip = !(m_acc >> 4 & 1); diff --git a/src/emu/cpu/ucom4/ucom4.c b/src/emu/cpu/ucom4/ucom4.c index 00a4167fa92..ab1e436c372 100644 --- a/src/emu/cpu/ucom4/ucom4.c +++ b/src/emu/cpu/ucom4/ucom4.c @@ -7,20 +7,34 @@ reference: 1981 NEC Microcomputers Catalog (later editions may have errors!) also looked at asterick's JavaScript D553 emulator for verification, with permission + TODO: + - what happens with uCOM-43 opcodes on an uCOM-44/45 MCU? + */ +enum +{ + NEC_UCOM43 = 0, + NEC_UCOM44, + NEC_UCOM45 +}; + #include "ucom4.h" #include "debugger.h" #include "ucom4op.inc" -// uCOM-43 products -const device_type NEC_D553 = &device_creator<upd553_cpu_device>; // 42-pin PMOS, 35 pins for I/O, Open Drain output, 2000x8 ROM, 96x4 RAM -const device_type NEC_D650 = &device_creator<upd650_cpu_device>; // 42-pin CMOS, 35 pins for I/O, push-pull output, 2000x8 ROM, 96x4 RAM +// uCOM-43 products: 2000x8 ROM, RAM size custom, supports full instruction set +const device_type NEC_D553 = &device_creator<upd553_cpu_device>; // 42-pin PMOS, 35 pins for I/O, Open Drain output, 96x4 RAM +const device_type NEC_D650 = &device_creator<upd650_cpu_device>; // 42-pin CMOS, 35 pins for I/O, push-pull output, 96x4 RAM + +// uCOM-44 products: 1000x8 ROM, 64x4 RAM, does not support external interrupt +const device_type NEC_D552 = &device_creator<upd552_cpu_device>; // 42-pin PMOS, 35 pins for I/O, Open Drain output + +// uCOM-45 products: ROM size custom, 32x4 RAM +//.. -// uCOM-44 products -const device_type NEC_D552 = &device_creator<upd552_cpu_device>; // 42-pin PMOS, 35 pins for I/O, Open Drain output, 1000x8 ROM, 64x4 RAM // internal memory maps static ADDRESS_MAP_START(program_1k, AS_PROGRAM, 8, ucom4_cpu_device) @@ -44,15 +58,15 @@ ADDRESS_MAP_END // device definitions upd553_cpu_device::upd553_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : ucom4_cpu_device(mconfig, NEC_D553, "uPD553", tag, owner, clock, 3, 11, ADDRESS_MAP_NAME(program_2k), 7, ADDRESS_MAP_NAME(data_96x4), "upd553", __FILE__) + : ucom4_cpu_device(mconfig, NEC_D553, "uPD553", tag, owner, clock, NEC_UCOM43, 3, 11, ADDRESS_MAP_NAME(program_2k), 7, ADDRESS_MAP_NAME(data_96x4), "upd553", __FILE__) { } upd650_cpu_device::upd650_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : ucom4_cpu_device(mconfig, NEC_D650, "uPD650", tag, owner, clock, 3, 11, ADDRESS_MAP_NAME(program_2k), 7, ADDRESS_MAP_NAME(data_96x4), "upd650", __FILE__) + : ucom4_cpu_device(mconfig, NEC_D650, "uPD650", tag, owner, clock, NEC_UCOM43, 3, 11, ADDRESS_MAP_NAME(program_2k), 7, ADDRESS_MAP_NAME(data_96x4), "upd650", __FILE__) { } upd552_cpu_device::upd552_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : ucom4_cpu_device(mconfig, NEC_D552, "uPD552", tag, owner, clock, 1, 10, ADDRESS_MAP_NAME(program_1k), 6, ADDRESS_MAP_NAME(data_64x4), "upd552", __FILE__) + : ucom4_cpu_device(mconfig, NEC_D552, "uPD552", tag, owner, clock, NEC_UCOM44, 1, 10, ADDRESS_MAP_NAME(program_1k), 6, ADDRESS_MAP_NAME(data_64x4), "upd552", __FILE__) { } @@ -64,11 +78,11 @@ void ucom4_cpu_device::state_string_export(const device_state_entry &entry, astr // obviously not from a single flags register case STATE_GENFLAGS: string.printf("%c%c%c%c%c", - m_inte_f ? 'E':'e', - m_int_f ? 'I':'i', - m_timer_f ? 'T':'t', - m_carry_s ? 'S':'s', - m_carry_f ? 'C':'c' + m_inte_f ? 'E':'e', + m_int_f ? 'I':'i', + m_timer_f ? 'T':'t', + m_carry_s_f ? 'S':'s', + m_carry_f ? 'C':'c' ); break; @@ -118,12 +132,14 @@ void ucom4_cpu_device::device_start() memset(m_stack, 0, sizeof(m_stack)); m_op = 0; m_prev_op = 0; + m_arg = 0; + m_skip = false; m_pc = 0; m_acc = 0; m_dpl = 0; m_dph = 0; m_carry_f = 0; - m_carry_s = 0; + m_carry_s_f = 0; m_timer_f = 0; m_int_f = 0; m_inte_f = 0; @@ -132,12 +148,14 @@ void ucom4_cpu_device::device_start() save_item(NAME(m_stack)); save_item(NAME(m_op)); save_item(NAME(m_prev_op)); + save_item(NAME(m_arg)); + save_item(NAME(m_skip)); save_item(NAME(m_pc)); save_item(NAME(m_acc)); save_item(NAME(m_dpl)); save_item(NAME(m_dph)); save_item(NAME(m_carry_f)); - save_item(NAME(m_carry_s)); + save_item(NAME(m_carry_s_f)); save_item(NAME(m_timer_f)); save_item(NAME(m_int_f)); save_item(NAME(m_inte_f)); @@ -165,6 +183,7 @@ void ucom4_cpu_device::device_reset() m_inte_f = 1; m_pc = 0; m_op = 0; + m_skip = false; } @@ -173,17 +192,134 @@ void ucom4_cpu_device::device_reset() // execute //------------------------------------------------- +void ucom4_cpu_device::fetch_arg() +{ + // 2-byte opcodes: STM/LDI/CLI/CI, JMP/CAL, OCD + if ((m_op & 0xfc) == 0x14 || (m_op & 0xf0) == 0xa0 || m_op == 0x1e) + { + m_icount--; + m_arg = m_program->read_byte(m_pc); + m_pc = (m_pc + 1) & m_prgmask; + } +} + void ucom4_cpu_device::execute_run() { while (m_icount > 0) { m_icount--; - + // remember previous opcode m_prev_op = m_op; debugger_instruction_hook(this, m_pc); m_op = m_program->read_byte(m_pc); m_pc = (m_pc + 1) & m_prgmask; + fetch_arg(); + + if (m_skip) + { + m_skip = false; + continue; + } + + switch (m_op & 0xf0) + { + case 0x80: op_ldz(); break; + case 0x90: op_li(); break; + case 0xa0: op_jmpcal(); break; + case 0xb0: op_czp(); break; + + case 0xc0: case 0xd0: case 0xe0: case 0xf0: op_jcp(); break; + + default: + switch (m_op) + { + case 0x00: op_nop(); break; + case 0x01: op_di(); break; + case 0x02: op_s(); break; + case 0x03: op_tit(); break; + case 0x04: op_tc(); break; + case 0x05: op_ttm(); break; + case 0x06: op_daa(); break; + case 0x07: op_tal(); break; + case 0x08: op_ad(); break; + case 0x09: op_ads(); break; + case 0x0a: op_das(); break; + case 0x0b: op_clc(); break; + case 0x0c: op_cm(); break; + case 0x0d: op_inc(); break; + case 0x0e: op_op(); break; + case 0x0f: op_dec(); break; + case 0x10: op_cma(); break; + case 0x11: op_cia(); break; + case 0x12: op_tla(); break; + case 0x13: op_ded(); break; + case 0x14: op_stm(); break; + case 0x15: op_ldi(); break; + case 0x16: op_cli(); break; + case 0x17: op_ci(); break; + case 0x18: op_exl(); break; + case 0x19: op_adc(); break; + case 0x1a: op_xc(); break; + case 0x1b: op_stc(); break; + case 0x1c: op_illegal(); break; + case 0x1d: op_inm(); break; + case 0x1e: op_ocd(); break; + case 0x1f: op_dem(); break; + + case 0x30: op_rar(); break; + case 0x31: op_ei(); break; + case 0x32: op_ip(); break; + case 0x33: op_ind(); break; + + case 0x40: op_ia(); break; + case 0x41: op_jpa(); break; + case 0x42: op_taz(); break; + case 0x43: op_taw(); break; + case 0x44: op_oe(); break; + case 0x45: op_illegal(); break; + case 0x46: op_tly(); break; + case 0x47: op_thx(); break; + case 0x48: op_rt(); break; + case 0x49: op_rts(); break; + case 0x4a: op_xaz(); break; + case 0x4b: op_xaw(); break; + case 0x4c: op_xls(); break; + case 0x4d: op_xhr(); break; + case 0x4e: op_xly(); break; + case 0x4f: op_xhx(); break; + + default: + switch (m_op & 0xfc) + { + case 0x20: op_fbf(); break; + case 0x24: op_tab(); break; + case 0x28: op_xm(); break; + case 0x2c: op_xmd(); break; + + case 0x34: op_cmb(); break; + case 0x38: op_lm(); break; + case 0x3c: op_xmi(); break; + + case 0x50: op_tpb(); break; + case 0x54: op_tpa(); break; + case 0x58: op_tmb(); break; + case 0x5c: op_fbt(); break; + case 0x60: op_rpb(); break; + case 0x64: op_reb(); break; + case 0x68: op_rmb(); break; + case 0x6c: op_rfb(); break; + case 0x70: op_spb(); break; + case 0x74: op_seb(); break; + case 0x78: op_smb(); break; + case 0x7c: op_sfb(); break; + } + break; // 0xfc + + } + break; // 0xff + + } // big switch } } diff --git a/src/emu/cpu/ucom4/ucom4.h b/src/emu/cpu/ucom4/ucom4.h index db0c3764a70..86042e4c682 100644 --- a/src/emu/cpu/ucom4/ucom4.h +++ b/src/emu/cpu/ucom4/ucom4.h @@ -50,12 +50,13 @@ class ucom4_cpu_device : public cpu_device { public: // construction/destruction - ucom4_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, int stack_levels, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char *shortname, const char *source) + ucom4_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, int family, int stack_levels, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char *shortname, const char *source) : cpu_device(mconfig, type, name, tag, owner, clock, shortname, source) , m_program_config("program", ENDIANNESS_BIG, 8, prgwidth, 0, program) , m_data_config("data", ENDIANNESS_BIG, 8, datawidth, 0, data) , m_prgwidth(prgwidth) , m_datawidth(datawidth) + , m_family(family) , m_stack_levels(stack_levels) , m_read_a(*this) , m_read_b(*this) @@ -94,6 +95,8 @@ protected: virtual UINT32 execute_max_cycles() const { return 2; } virtual UINT32 execute_input_lines() const { return 1; } virtual void execute_run(); + + void fetch_arg(); // device_memory_interface overrides virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return(spacenum == AS_PROGRAM) ? &m_program_config :((spacenum == AS_DATA) ? &m_data_config : NULL); } @@ -102,6 +105,7 @@ protected: virtual UINT32 disasm_min_opcode_bytes() const { return 1; } virtual UINT32 disasm_max_opcode_bytes() const { return 2; } virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + void state_string_export(const device_state_entry &entry, astring &string); address_space_config m_program_config; @@ -113,11 +117,13 @@ protected: int m_datawidth; int m_prgmask; int m_datamask; + int m_family; // MCU family (43/44/45) int m_stack_levels; // number of callstack levels UINT16 m_stack[3]; // max 3 - UINT8 m_op; - UINT8 m_prev_op; + UINT8 m_prev_op; // previous opcode + UINT8 m_arg; // opcode argument for 2-byte opcodes + bool m_skip; // skip next opcode int m_icount; UINT16 m_pc; // program counter @@ -125,7 +131,7 @@ protected: UINT8 m_dpl; // 4-bit data pointer low (RAM x) UINT8 m_dph; // 1/2/3-bit data pointer high (RAM y) UINT8 m_carry_f; // carry flag - UINT8 m_carry_s; // carry save + UINT8 m_carry_s_f; // carry save flag UINT8 m_timer_f; // timer out flag UINT8 m_int_f; // interrupt flag UINT8 m_inte_f; // interrupt enable flag @@ -143,6 +149,92 @@ protected: devcb_write8 m_write_g; devcb_write8 m_write_h; devcb_write8 m_write_i; + + // opcode handlers + void op_illegal(); + bool check_op_43(); + + void op_li(); + void op_lm(); + void op_ldi(); + void op_ldz(); + void op_s(); + void op_tal(); + void op_tla(); + + void op_xm(); + void op_xmi(); + void op_xmd(); + void op_ad(); + void op_adc(); + void op_ads(); + void op_daa(); + void op_das(); + + void op_exl(); + void op_cma(); + void op_cia(); + void op_clc(); + void op_stc(); + void op_tc(); + void op_inc(); + void op_dec(); + void op_ind(); + void op_ded(); + + void op_rmb(); + void op_smb(); + void op_reb(); + void op_seb(); + void op_rpb(); + void op_spb(); + void op_jmpcal(); + void op_jcp(); + void op_jpa(); + void op_czp(); + void op_rt(); + void op_rts(); + + void op_ci(); + void op_cm(); + void op_cmb(); + void op_tab(); + void op_cli(); + void op_tmb(); + void op_tpa(); + void op_tpb(); + + void op_tit(); + void op_ia(); + void op_ip(); + void op_oe(); + void op_op(); + void op_ocd(); + void op_nop(); + + void op_taw(); + void op_taz(); + void op_thx(); + void op_tly(); + void op_xaw(); + void op_xaz(); + void op_xhr(); + void op_xhx(); + void op_xls(); + void op_xly(); + void op_xc(); + + void op_sfb(); + void op_rfb(); + void op_fbt(); + void op_fbf(); + void op_rar(); + void op_inm(); + void op_dem(); + void op_stm(); + void op_ttm(); + void op_ei(); + void op_di(); }; diff --git a/src/emu/cpu/ucom4/ucom4op.inc b/src/emu/cpu/ucom4/ucom4op.inc index ebb932edb2d..0ae6c88ce9b 100644 --- a/src/emu/cpu/ucom4/ucom4op.inc +++ b/src/emu/cpu/ucom4/ucom4op.inc @@ -1 +1,579 @@ -// uCOM4 opcode handlers +// uCOM-4 opcode handlers + +// internal helpers + +void ucom4_cpu_device::op_illegal() +{ + logerror("%s unknown opcode $%02X at $%03X\n", tag(), m_op, m_pc); +} + + + +// basic instruction set + +// Load + +void ucom4_cpu_device::op_li() +{ + // LI X: Load ACC with X + // note: only execute the first one in a sequence of LAI + if ((m_prev_op & 0xf0) != (m_op & 0xf0)) + m_acc = m_op & 0x0f; +} + +void ucom4_cpu_device::op_lm() +{ + // LM X: Load ACC with RAM, xor DPh with X + op_illegal(); +} + +void ucom4_cpu_device::op_ldi() +{ + // LDI X: Load DP with X + op_illegal(); +} + +void ucom4_cpu_device::op_ldz() +{ + // LDZ X: Load DPh with 0, Load DPl with X + op_illegal(); +} + + +// Store + +void ucom4_cpu_device::op_s() +{ + // S: Store ACC into RAM + op_illegal(); +} + + +// Transfer + +void ucom4_cpu_device::op_tal() +{ + // TAL: Transfer ACC to DPl + op_illegal(); +} + +void ucom4_cpu_device::op_tla() +{ + // TLA: Transfer + op_illegal(); +} + + +// Exchange + +void ucom4_cpu_device::op_xm() +{ + // XM X: Exchange ACC with RAM, xor DPh with X + op_illegal(); +} + +void ucom4_cpu_device::op_xmi() +{ + // XMI X: Exchange ACC with RAM, xor DPh with X, Increment DPl, skip next on carry + op_illegal(); +} + +void ucom4_cpu_device::op_xmd() +{ + // XMD X: Exchange ACC with RAM, xor DPh with X, Decrement DPl, skip next on carry + op_illegal(); +} + + +// Arithmetic + +void ucom4_cpu_device::op_ad() +{ + // AD: Add RAM to Acc, skip next on carry + op_illegal(); +} + +void ucom4_cpu_device::op_adc() +{ + // ADC: Add RAM and carry to Acc, store Carry F/F + op_illegal(); +} + +void ucom4_cpu_device::op_ads() +{ + // ADS: Add RAM and carry to Acc, store Carry F/F, skip next on carry + op_illegal(); +} + +void ucom4_cpu_device::op_daa() +{ + // DAA: Add 6 to ACC to adjust decimal for BCD Addition + op_illegal(); +} + +void ucom4_cpu_device::op_das() +{ + // DAS: Add 10 to ACC to adjust decimal for BCD Subtraction + op_illegal(); +} + + +// Logical + +void ucom4_cpu_device::op_exl() +{ + // EXL: Xor ACC with RAM + op_illegal(); +} + + +// Accumulator + +void ucom4_cpu_device::op_cma() +{ + // CMA: Complement ACC + op_illegal(); +} + +void ucom4_cpu_device::op_cia() +{ + // CIA: Complement ACC, Increment ACC + op_illegal(); +} + + +// Carry Flag + +void ucom4_cpu_device::op_clc() +{ + // CLC: Reset Carry F/F + op_illegal(); +} + +void ucom4_cpu_device::op_stc() +{ + // STC: Set Carry F/F + op_illegal(); +} + +void ucom4_cpu_device::op_tc() +{ + // TC: skip next on Carry F/F + op_illegal(); +} + + +// Increment and Decrement + +void ucom4_cpu_device::op_inc() +{ + // INC: Increment ACC, skip next on carry + op_illegal(); +} + +void ucom4_cpu_device::op_dec() +{ + // DEC: Decrement ACC, skip next on carry + op_illegal(); +} + +void ucom4_cpu_device::op_ind() +{ + // IND: Increment DPl, skip next on carry + op_illegal(); +} + +void ucom4_cpu_device::op_ded() +{ + // DED: Decrement DPl, skip next on carry + op_illegal(); +} + + +// Bit Manipulation + +void ucom4_cpu_device::op_rmb() +{ + // RMB B: Reset a single bit of RAM + op_illegal(); +} + +void ucom4_cpu_device::op_smb() +{ + // SMB B: Set a single bit of RAM + op_illegal(); +} + +void ucom4_cpu_device::op_reb() +{ + // REB B: Reset a single bit of output port E + op_illegal(); +} + +void ucom4_cpu_device::op_seb() +{ + // SEB B: Set a single bit of output port E + op_illegal(); +} + +void ucom4_cpu_device::op_rpb() +{ + // RPB B: Reset a single bit of output port (DPl) + op_illegal(); +} + +void ucom4_cpu_device::op_spb() +{ + // SPB B: Set a single bit of output port (DPl) + op_illegal(); +} + + +// Jump, Call and Return + +void ucom4_cpu_device::op_jmpcal() +{ + // JMP A: Jump to Address / CAL A: Call Address + op_illegal(); +} + +void ucom4_cpu_device::op_jcp() +{ + // JCP A: Jump to Address in current page + op_illegal(); +} + +void ucom4_cpu_device::op_jpa() +{ + // JPA: Jump to (ACC) + op_illegal(); +} + +void ucom4_cpu_device::op_czp() +{ + // CZP A: Call (Address) + op_illegal(); +} + +void ucom4_cpu_device::op_rt() +{ + // RT: Return from subroutine + op_illegal(); +} + +void ucom4_cpu_device::op_rts() +{ + // RTS: Return from subroutine, skip next + op_rt(); + m_skip = true; +} + + +// Skip + +void ucom4_cpu_device::op_ci() +{ + // CI X: skip next on ACC equals X + op_illegal(); +} + +void ucom4_cpu_device::op_cm() +{ + // CM: skip next on ACC equals RAM + op_illegal(); +} + +void ucom4_cpu_device::op_cmb() +{ + // CMB B: skip next on bit(ACC) equals bit(RAM) + op_illegal(); +} + +void ucom4_cpu_device::op_tab() +{ + // TAB B: skip next on bit(ACC) + op_illegal(); +} + +void ucom4_cpu_device::op_cli() +{ + // CLI X: skip next on DPl equals X + op_illegal(); +} + +void ucom4_cpu_device::op_tmb() +{ + // TMB B: skip next on bit(RAM) + op_illegal(); +} + +void ucom4_cpu_device::op_tpa() +{ + // TPA B: skip next on bit(input port A) + op_illegal(); +} + +void ucom4_cpu_device::op_tpb() +{ + // TPB B: skip next on bit(input port (DPl)) + op_illegal(); +} + + +// Interrupt + +void ucom4_cpu_device::op_tit() +{ + // TIT: skip next on Interrupt F/F, reset Interrupt F/F + op_illegal(); +} + + +// Parallel I/O + +void ucom4_cpu_device::op_ia() +{ + // IA: x + op_illegal(); +} + +void ucom4_cpu_device::op_ip() +{ + // IP: x + op_illegal(); +} + +void ucom4_cpu_device::op_oe() +{ + // OE: x + op_illegal(); +} + +void ucom4_cpu_device::op_op() +{ + // OP: x + op_illegal(); +} + +void ucom4_cpu_device::op_ocd() +{ + // OCD X: x + op_illegal(); +} + + +// CPU Control + +void ucom4_cpu_device::op_nop() +{ + // NOP: No Operation +} + + + +// uCOM-43 extended instructions + +inline bool ucom4_cpu_device::check_op_43() +{ + // these opcodes are officially only supported on uCOM-43 + if (m_family != NEC_UCOM43) + logerror("%s using uCOM-43 opcode $%02X at $%03X\n", tag(), m_op, m_pc); + + return (m_family == NEC_UCOM43); +} + +// Transfer + +void ucom4_cpu_device::op_taw() +{ + if (!check_op_43()) return; + + // TAW: Transfer ACC to W + op_illegal(); +} + +void ucom4_cpu_device::op_taz() +{ + if (!check_op_43()) return; + + // TAZ: Transfer ACC to Z + op_illegal(); +} + +void ucom4_cpu_device::op_thx() +{ + if (!check_op_43()) return; + + // THX: Transfer DPh to X + op_illegal(); +} + +void ucom4_cpu_device::op_tly() +{ + if (!check_op_43()) return; + + // TLY: Transfer DPl to Y + op_illegal(); +} + + +// Exchange + +void ucom4_cpu_device::op_xaw() +{ + if (!check_op_43()) return; + + // XAW: Exchange ACC with W + op_illegal(); +} + +void ucom4_cpu_device::op_xaz() +{ + if (!check_op_43()) return; + + // XAZ: Exchange ACC with Z + op_illegal(); +} + +void ucom4_cpu_device::op_xhr() +{ + if (!check_op_43()) return; + + // XHR: Exchange DPh with R + op_illegal(); +} + +void ucom4_cpu_device::op_xhx() +{ + if (!check_op_43()) return; + + // XHX: Exchange DPh with X + op_illegal(); +} + +void ucom4_cpu_device::op_xls() +{ + if (!check_op_43()) return; + + // XLS: Exchange DPl with S + op_illegal(); +} + +void ucom4_cpu_device::op_xly() +{ + if (!check_op_43()) return; + + // XLY: Exchange DPl with Y + op_illegal(); +} + +void ucom4_cpu_device::op_xc() +{ + if (!check_op_43()) return; + + // XC: Exchange Carry F/F with Carry Save F/F + op_illegal(); +} + + +// Flag + +void ucom4_cpu_device::op_sfb() +{ + if (!check_op_43()) return; + + // SFB B: Set a single bit of FLAG + op_illegal(); +} + +void ucom4_cpu_device::op_rfb() +{ + if (!check_op_43()) return; + + // RFB B: Reset a single bit of FLAG + op_illegal(); +} + +void ucom4_cpu_device::op_fbt() +{ + if (!check_op_43()) return; + + // FBT B: skip next on bit(FLAG) + op_illegal(); +} + +void ucom4_cpu_device::op_fbf() +{ + if (!check_op_43()) return; + + // FBF B: skip next on not bit(FLAG) + op_illegal(); +} + + +// Accumulator + +void ucom4_cpu_device::op_rar() +{ + if (!check_op_43()) return; + + // RAR: Rotate ACC Right through Carry F/F + op_illegal(); +} + + +// Increment and Decrement + +void ucom4_cpu_device::op_inm() +{ + if (!check_op_43()) return; + + // INM: Increment RAM, skip next on carry + op_illegal(); +} + +void ucom4_cpu_device::op_dem() +{ + if (!check_op_43()) return; + + // DEM: Decrement RAM, skip next on carry + op_illegal(); +} + + +// Timer + +void ucom4_cpu_device::op_stm() +{ + if (!check_op_43()) return; + + // STM X: Reset Timer F/F, Start Timer with X + op_illegal(); +} + +void ucom4_cpu_device::op_ttm() +{ + if (!check_op_43()) return; + + // TTM: skip next on Timer F/F + op_illegal(); +} + + +// Interrupt + +void ucom4_cpu_device::op_ei() +{ + if (!check_op_43()) return; + + // EI: Set Interrupt Enable F/F + op_illegal(); +} + +void ucom4_cpu_device::op_di() +{ + if (!check_op_43()) return; + + // DI: Reset Interrupt Enable F/F + op_illegal(); +} |