summaryrefslogtreecommitdiffstatshomepage
diff options
context:
space:
mode:
author Brice Onken <32155223+briceonk@users.noreply.github.com>2022-02-27 16:31:50 -0800
committer GitHub <noreply@github.com>2022-02-28 07:31:50 +0700
commit8b97203256da2a1a04c6a2c1eb41d173b27edb0e (patch)
tree130014e9d6d97bec02503782d64a2a8238820578
parent405ba9f4e80c045859255118b18bd0c43433d335 (diff)
r4000.cpp: Set TLB global bit in EntryLo0/1 on TLBR instruction (#9348)
-rw-r--r--src/devices/cpu/mips/r4000.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/devices/cpu/mips/r4000.cpp b/src/devices/cpu/mips/r4000.cpp
index 2b12a2089f5..fd98bf5b834 100644
--- a/src/devices/cpu/mips/r4000.cpp
+++ b/src/devices/cpu/mips/r4000.cpp
@@ -1512,8 +1512,9 @@ void r4000_base_device::cp0_tlbr()
m_cp0[CP0_PageMask] = entry.mask;
m_cp0[CP0_EntryHi] = entry.vpn;
- m_cp0[CP0_EntryLo0] = entry.pfn[0];
- m_cp0[CP0_EntryLo1] = entry.pfn[1];
+ u64 const global = (entry.vpn & EH_G) ? EL_G : 0x0;
+ m_cp0[CP0_EntryLo0] = entry.pfn[0] | global;
+ m_cp0[CP0_EntryLo1] = entry.pfn[1] | global;
}
}