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author | 2019-10-14 19:10:45 +0700 | |
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committer | 2019-10-14 19:10:45 +0700 | |
commit | 84a61fd14fa7c24695234bc8bcf3fe74b6291ec1 (patch) | |
tree | 425bbcba0ba341f0fea82d018af4e499020f44ad | |
parent | 439605cee63caabe77eb30c0b3265e7715995c02 (diff) |
wtl3132: float operation condition (nw)
-rw-r--r-- | src/devices/machine/wtl3132.cpp | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/devices/machine/wtl3132.cpp b/src/devices/machine/wtl3132.cpp index 7fdfc61a8b3..64bd5a7942f 100644 --- a/src/devices/machine/wtl3132.cpp +++ b/src/devices/machine/wtl3132.cpp @@ -323,6 +323,19 @@ void wtl3132_device::stage3(unsigned const index) m_cr = (m_aa_in[1].v & 0xff000000) && (~m_aa_in[1].v & 0xff000000); m_a_out = i32_to_f32(m_aa_in[1].v); + + /* + * HACK: documentation specifies that the float instruction sets + * the condition register when ENCN=1, M1=1 and the operand sign + * bits are inconsistent. It does not say what should happen for + * other values of ENCN, however setting the condition register to + * indicate the result is less than zero like other ALU operations + * appears to be required by the SGI GR1 DMA microcode (and some + * other assumptions made there). + */ + if (OPF(code, ENCN) == 2) + m_cr = f32_lt(m_a_out, i32_to_f32(0)); + LOG("slot %d stage 3 float 0x%08x == %f\n", index, m_aa_in[1].v, u2f(m_a_out.v)); break; case MF_FIX: |