diff options
author | 2020-06-28 11:54:14 -0600 | |
---|---|---|
committer | 2020-06-28 11:54:14 -0600 | |
commit | 7016f2a641fad989b55cb867f0610ea8923c0b00 (patch) | |
tree | 809c7dd026233ed663123cfe7d7956b944ea1179 | |
parent | b8d165d17d51e5cea1a01bec8ee6f9396a4d104d (diff) |
mips3: Removed depricated DRC flag and add a flag to disable intrablock branching
-rw-r--r-- | src/devices/cpu/mips/mips3.h | 4 | ||||
-rw-r--r-- | src/devices/cpu/mips/mips3drc.cpp | 6 |
2 files changed, 7 insertions, 3 deletions
diff --git a/src/devices/cpu/mips/mips3.h b/src/devices/cpu/mips/mips3.h index 9478f6b39c7..0657a511a48 100644 --- a/src/devices/cpu/mips/mips3.h +++ b/src/devices/cpu/mips/mips3.h @@ -974,11 +974,11 @@ COMPILER-SPECIFIC OPTIONS #define MIPS3DRC_STRICT_COP0 0x0002 /* validate all COP0 instructions */ #define MIPS3DRC_STRICT_COP1 0x0004 /* validate all COP1 instructions */ #define MIPS3DRC_STRICT_COP2 0x0008 /* validate all COP2 instructions */ -#define MIPS3DRC_FLUSH_PC 0x0010 /* flush the PC value before each memory access */ +#define MIPS3DRC_DISABLE_INTRABLOCK 0x0010 /* disable intrablock branching */ #define MIPS3DRC_CHECK_OVERFLOWS 0x0020 /* actually check overflows on add/sub instructions */ #define MIPS3DRC_ACCURATE_DIVZERO 0x0040 /* load correct values into HI/LO on integer divide-by-zero */ -#define MIPS3DRC_COMPATIBLE_OPTIONS (MIPS3DRC_STRICT_VERIFY | MIPS3DRC_STRICT_COP1 | MIPS3DRC_STRICT_COP0 | MIPS3DRC_STRICT_COP2 | MIPS3DRC_FLUSH_PC) +#define MIPS3DRC_COMPATIBLE_OPTIONS (MIPS3DRC_STRICT_VERIFY | MIPS3DRC_STRICT_COP1 | MIPS3DRC_STRICT_COP0 | MIPS3DRC_STRICT_COP2) #define MIPS3DRC_FASTEST_OPTIONS (0) diff --git a/src/devices/cpu/mips/mips3drc.cpp b/src/devices/cpu/mips/mips3drc.cpp index 0f1cd0a29d4..665f7b1a0b4 100644 --- a/src/devices/cpu/mips/mips3drc.cpp +++ b/src/devices/cpu/mips/mips3drc.cpp @@ -1247,6 +1247,8 @@ void mips3_device::generate_sequence_instruction(drcuml_block &block, compiler_s UML_CALLC(block, cfunc_printf_debug, this); // callc printf_debug } UML_EXH(block, *m_tlb_mismatch, 0); // exh tlb_mismatch,0 + // Unconditional tlb exception, no point going further + return; } /* validate our TLB entry at this PC; if we fail, we need to handle it */ @@ -1280,6 +1282,8 @@ void mips3_device::generate_sequence_instruction(drcuml_block &block, compiler_s UML_CALLC(block, cfunc_printf_debug, this); // callc printf_debug } UML_EXH(block, *m_tlb_mismatch, 0); // exh tlb_mismatch,0 + // Unconditional tlb exception, no point going further + return; } } @@ -1331,7 +1335,7 @@ void mips3_device::generate_delay_slot_and_branch(drcuml_block &block, compiler_ if (desc->targetpc != BRANCH_TARGET_DYNAMIC) { generate_update_cycles(block, compiler_temp, desc->targetpc, true); // <subtract cycles> - if (desc->flags & OPFLAG_INTRABLOCK_BRANCH) + if (!(m_drcoptions & MIPS3DRC_DISABLE_INTRABLOCK) && desc->flags & OPFLAG_INTRABLOCK_BRANCH) { UML_JMP(block, desc->targetpc | 0x80000000); // jmp desc->targetpc | 0x80000000 } |