diff options
author | 2022-02-15 19:26:17 +0700 | |
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committer | 2022-02-15 19:26:17 +0700 | |
commit | 38970344122f1eaa9530bfe10fe1e5b072e30ccd (patch) | |
tree | 970213cf9a15a5e0ff7a5a882f0c7c7d5cc72fe8 | |
parent | 406e4421481a269054129149ff2c34b0ffe50f29 (diff) |
mips3: fix some bugs
-rw-r--r-- | src/devices/cpu/mips/mips3.cpp | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/src/devices/cpu/mips/mips3.cpp b/src/devices/cpu/mips/mips3.cpp index f34de33c24f..924ce3aa634 100644 --- a/src/devices/cpu/mips/mips3.cpp +++ b/src/devices/cpu/mips/mips3.cpp @@ -345,11 +345,9 @@ void mips3_device::generate_exception(int exception, int backup) void mips3_device::generate_tlb_exception(int exception, offs_t address) { m_core->cpr[0][COP0_BadVAddr] = address; - if(exception == EXCEPTION_TLBLOAD || exception == EXCEPTION_TLBSTORE || exception == EXCEPTION_TLBLOAD_FILL || exception == EXCEPTION_TLBSTORE_FILL) - { - m_core->cpr[0][COP0_Context] = (m_core->cpr[0][COP0_Context] & 0xff800000) | ((address >> 9) & 0x007ffff0); - m_core->cpr[0][COP0_EntryHi] = (address & 0xffffe000) | (m_core->cpr[0][COP0_EntryHi] & 0xff); - } + m_core->cpr[0][COP0_Context] = (m_core->cpr[0][COP0_Context] & 0xff800000) | ((address >> 9) & 0x007ffff0); + m_core->cpr[0][COP0_EntryHi] = (address & 0xffffe000) | (m_core->cpr[0][COP0_EntryHi] & 0xff); + generate_exception(exception, 1); } @@ -1720,7 +1718,7 @@ void mips3_device::set_cop0_reg(int idx, uint64_t val) { case COP0_Cause: CAUSE = (CAUSE & 0xfc00) | (val & ~0xfc00); - if (CAUSE & 0x300) + if ((CAUSE & SR & 0x300) && (SR & SR_IE) && !(SR & (SR_EXL | SR_ERL))) { /* if we're in a delay slot, propogate the target PC before generating the exception */ if (m_nextpc != ~0) @@ -5208,9 +5206,8 @@ void mips3_device::execute_run() m_core->llbit = 1; if LL_BREAK machine().debug_break(); - break; } - [[fallthrough]]; + break; case 0x31: /* LWC1 */ if (!(SR & SR_COP1)) { @@ -5231,9 +5228,8 @@ void mips3_device::execute_run() m_core->llbit = 1; if LL_BREAK machine().debug_break(); - break; } - [[fallthrough]]; + break; case 0x35: /* LDC1 */ if (!(SR & SR_COP1)) { |