diff options
author | mamehaze <mamehaze@users.noreply.github.com> | 2015-03-08 11:56:50 +0000 |
---|---|---|
committer | mamehaze <mamehaze@users.noreply.github.com> | 2015-03-08 11:56:50 +0000 |
commit | 37bf50f2bc986137f403f03ca3400e3545d8cce4 (patch) | |
tree | 6fe040dc38e8321addb4c089a167b75ddde45118 | |
parent | 075cb81413157042ef5832d93879297eeb671bd0 (diff) |
few bits of v53 stuff, start dynamic peripheral mapping, attempts to set up timers at least (nw)
-rw-r--r-- | src/emu/cpu/nec/v53.c | 221 | ||||
-rw-r--r-- | src/emu/cpu/nec/v53.h | 27 | ||||
-rw-r--r-- | src/mame/audio/hng64.c | 6 |
3 files changed, 231 insertions, 23 deletions
diff --git a/src/emu/cpu/nec/v53.c b/src/emu/cpu/nec/v53.c index 0952984f1cf..8cdf02c01b5 100644 --- a/src/emu/cpu/nec/v53.c +++ b/src/emu/cpu/nec/v53.c @@ -79,41 +79,220 @@ WRITE8_MEMBER(v53_base_device::WCY4_w) WRITE8_MEMBER(v53_base_device::SULA_w) { printf("v53: SULA_w %02x\n", data); + m_SULA = data; + install_peripheral_io(); } WRITE8_MEMBER(v53_base_device::TULA_w) { printf("v53: TULA_w %02x\n", data); + m_TULA = data; + install_peripheral_io(); } WRITE8_MEMBER(v53_base_device::IULA_w) { printf("v53: IULA_w %02x\n", data); + m_IULA = data; + install_peripheral_io(); } WRITE8_MEMBER(v53_base_device::DULA_w) { printf("v53: DULA_w %02x\n", data); + m_DULA = data; + install_peripheral_io(); } WRITE8_MEMBER(v53_base_device::OPHA_w) { printf("v53: OPHA_w %02x\n", data); + m_OPHA = data; + install_peripheral_io(); } WRITE8_MEMBER(v53_base_device::OPSEL_w) { printf("v53: OPSEL_w %02x\n", data); + m_OPSEL = data; + install_peripheral_io(); } WRITE8_MEMBER(v53_base_device::SCTL_w) { + // bit 7: unused + // bit 6: unused + // bit 5: unused + // bit 4: SCU input clock source + // bit 3: uPD71037 DMA mode - Carry A20 + // bit 2: uPD71037 DMA mode - Carry A16 + // bit 1: uPD71037 DMA mode enable (otherwise in uPD71071 mode) + // bit 0: Onboard pripheral I/O maps to 8-bit boundaries? (otherwise 16-bit) + printf("v53: SCTL_w %02x\n", data); + m_SCTL = data; + install_peripheral_io(); +} +/* +m_WCY0 = 0x07; +m_WCY1 = 0x77; +m_WCY2 = 0x77; +m_WCY3 = 0x77; +m_WCY4 = 0x77; +m_WMB0 = 0x77; +m_WMB1 = 0x77; +m_WAC = 0x00; +m_TCKS = 0x00; +m_RFC = 0x80; +m_SBCR = 0x00; +m_BRC = 0x00; +// SCU +m_SMD = 0x4b; +m_SCM = 0x00; +m_SIMK = 0x03; +m_SST = 0x04; +// DMA +m_DCH = 0x01; +m_DMD = 0x00; +m_DCC = 0x0000; +m_DST = 0x00; +m_DMK = 0x0f; +*/ + +void v53_base_device::device_reset() +{ + nec_common_device::device_reset(); + + m_SCTL = 0x00; + m_OPSEL= 0x00; + + // peripheral addresses + m_SULA = 0x00; + m_TULA = 0x00; + m_IULA = 0x00; + m_DULA = 0x00; + m_OPHA = 0x00; + } +void v53_base_device::device_start() +{ + nec_common_device::device_start(); +} + +void v53_base_device::install_peripheral_io() +{ + // unmap everything in I/O space up to the fixed position registers (we avoid overwriting them, it isn't a valid config) + space(AS_IO).unmap_readwrite(0x0000, 0xfeff); + + // IOAG determines if the handlers used 8-bit or 16-bit access + // the hng64.c games first set everything up in 8-bit mode, then + // do the procedure again in 16-bit mode before using them?! + + int IOAG = m_SCTL & 1; + + if (m_OPSEL & 0x01) // DMA Unit available + { + if (IOAG) // 8-bit + { + + } + else + { + + } + } + + if (m_OPSEL & 0x02) // Interupt Control Unit available + { + if (IOAG) // 8-bit + { + + } + else + { + + } + } + + if (m_OPSEL & 0x04) // Timer Control Unit available + { + UINT16 base = (m_OPHA << 8) | m_TULA; + printf("installing TCU to %04x\n", base); + + if (IOAG) // 8-bit + { + + } + else + { + space(AS_IO).install_readwrite_handler(base+0x00, base+0x01, read8_delegate(FUNC(v53_base_device::tmu_tst0_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct0_w), this), 0x00ff); + space(AS_IO).install_readwrite_handler(base+0x02, base+0x03, read8_delegate(FUNC(v53_base_device::tmu_tst1_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct1_w), this), 0x00ff); + space(AS_IO).install_readwrite_handler(base+0x04, base+0x05, read8_delegate(FUNC(v53_base_device::tmu_tst2_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct2_w), this), 0x00ff); + space(AS_IO).install_write_handler(base+0x06, base+0x07, write8_delegate(FUNC(v53_base_device::tmu_tmd_w), this), 0x00ff); + } + } + + if (m_OPSEL & 0x08) // Serial Control Unit available + { + + if (IOAG) // 8-bit + { + + } + else + { + + } + } + +} + +/*** TCU ***/ + +READ8_MEMBER(v53_base_device::tmu_tst0_r) +{ + printf("v53: tmu_tst0_r\n"); + return 0; +} + +WRITE8_MEMBER(v53_base_device::tmu_tct0_w) +{ + printf("v53: tmu_tct0_w %02x\n", data); +} + +READ8_MEMBER(v53_base_device::tmu_tst1_r) +{ + printf("v53: tmu_tst1_r\n"); + return 0; +} + +WRITE8_MEMBER(v53_base_device::tmu_tct1_w) +{ + printf("v53: tmu_tct1_w %02x\n", data); +} + +READ8_MEMBER(v53_base_device::tmu_tst2_r) +{ + printf("v53: tmu_tst2_r\n"); + return 0; +} + +WRITE8_MEMBER(v53_base_device::tmu_tct2_w) +{ + printf("v53: tmu_tct2_w %02x\n", data); +} + +WRITE8_MEMBER(v53_base_device::tmu_tmd_w) +{ + printf("v53: tmu_tmd_w %02x\n", data); +} + +/* General stuff */ + static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device ) - AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BSEL_w, 0x00ff) // 0xffe0 - AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BADR_w, 0xff00) // 0xffe1 + AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BSEL_w, 0x00ff) // 0xffe0 // uPD71037 DMA mode bank selection register + AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BADR_w, 0xff00) // 0xffe1 // uPD71037 DMA mode bank register peripheral mapping (also uses OPHA) // AM_RANGE(0xffe2, 0xffe3) // (reserved , 0x00ff) // 0xffe2 // AM_RANGE(0xffe2, 0xffe3) // (reserved , 0xff00) // 0xffe3 // AM_RANGE(0xffe4, 0xffe5) // (reserved , 0x00ff) // 0xffe4 @@ -121,28 +300,28 @@ static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device ) // AM_RANGE(0xffe6, 0xffe7) // (reserved , 0x00ff) // 0xffe6 // AM_RANGE(0xffe6, 0xffe7) // (reserved , 0xff00) // 0xffe7 // AM_RANGE(0xffe8, 0xffe9) // (reserved , 0x00ff) // 0xffe8 - AM_RANGE(0xffe8, 0xffe9) AM_WRITE8( BRC_w , 0xff00) // 0xffe9 - AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WMB0_w, 0x00ff) // 0xffea - AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WCY1_w, 0xff00) // 0xffeb - AM_RANGE(0xffec, 0xffed) AM_WRITE8( WCY0_w, 0x00ff) // 0xffec - AM_RANGE(0xffec, 0xffed) AM_WRITE8( WAC_w, 0xff00) // 0xffed + AM_RANGE(0xffe8, 0xffe9) AM_WRITE8( BRC_w , 0xff00) // 0xffe9 // baud rate counter (used for serial peripheral) + AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WMB0_w, 0x00ff) // 0xffea // waitstate control + AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WCY1_w, 0xff00) // 0xffeb // waitstate control + AM_RANGE(0xffec, 0xffed) AM_WRITE8( WCY0_w, 0x00ff) // 0xffec // waitstate control + AM_RANGE(0xffec, 0xffed) AM_WRITE8( WAC_w, 0xff00) // 0xffed // waitstate control // AM_RANGE(0xffee, 0xffef) // (reserved , 0x00ff) // 0xffee // AM_RANGE(0xffee, 0xffef) // (reserved , 0xff00) // 0xffef - AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( TCKS_w, 0x00ff) // 0xfff0 - AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( SBCR_w, 0xff00) // 0xfff1 - AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( REFC_w, 0x00ff) // 0xfff2 - AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( WMB1_w, 0xff00) // 0xfff3 - AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY2_w, 0x00ff) // 0xfff4 - AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY3_w, 0xff00) // 0xfff5 - AM_RANGE(0xfff6, 0xfff7) AM_WRITE8( WCY4_w, 0x00ff) // 0xfff6 + AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( TCKS_w, 0x00ff) // 0xfff0 // timer clocks + AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( SBCR_w, 0xff00) // 0xfff1 // internal clock divider, halt behavior etc. + AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( REFC_w, 0x00ff) // 0xfff2 // ram refresh control + AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( WMB1_w, 0xff00) // 0xfff3 // waitstate control + AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY2_w, 0x00ff) // 0xfff4 // waitstate control + AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY3_w, 0xff00) // 0xfff5 // waitstate control + AM_RANGE(0xfff6, 0xfff7) AM_WRITE8( WCY4_w, 0x00ff) // 0xfff6 // waitstate control // AM_RANGE(0xfff6, 0xfff7) // (reserved , 0xff00) // 0xfff7 - AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( SULA_w, 0x00ff) // 0xfff8 - AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( TULA_w, 0xff00) // 0xfff9 - AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( IULA_w, 0x00ff) // 0xfffa - AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( DULA_w, 0xff00) // 0xfffb - AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPHA_w, 0x00ff) // 0xfffc - AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPSEL_w, 0xff00) // 0xfffd - AM_RANGE(0xfffe, 0xffff) AM_WRITE8( SCTL_w, 0x00ff) // 0xfffe + AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( SULA_w, 0x00ff) // 0xfff8 // peripheral mapping + AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( TULA_w, 0xff00) // 0xfff9 // peripheral mapping + AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( IULA_w, 0x00ff) // 0xfffa // peripheral mapping + AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( DULA_w, 0xff00) // 0xfffb // peripheral mapping + AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPHA_w, 0x00ff) // 0xfffc // peripheral mapping (upper bits, common) + AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPSEL_w, 0xff00) // 0xfffd // peripheral enabling + AM_RANGE(0xfffe, 0xffff) AM_WRITE8( SCTL_w, 0x00ff) // 0xfffe // peripheral configuration (& byte / word mapping) // AM_RANGE(0xfffe, 0xffff) // (reserved , 0xff00) // 0xffff ADDRESS_MAP_END diff --git a/src/emu/cpu/nec/v53.h b/src/emu/cpu/nec/v53.h index 9214fbf3652..2248d8036c6 100644 --- a/src/emu/cpu/nec/v53.h +++ b/src/emu/cpu/nec/v53.h @@ -30,8 +30,28 @@ public: DECLARE_WRITE8_MEMBER(OPSEL_w); DECLARE_WRITE8_MEMBER(SCTL_w); - const address_space_config m_io_space_config; + UINT8 m_SCTL; + UINT8 m_OPSEL; + + UINT8 m_SULA; + UINT8 m_TULA; + UINT8 m_IULA; + UINT8 m_DULA; + UINT8 m_OPHA; + + // TMU + DECLARE_READ8_MEMBER(tmu_tst0_r); + DECLARE_WRITE8_MEMBER(tmu_tct0_w); + DECLARE_READ8_MEMBER(tmu_tst1_r); + DECLARE_WRITE8_MEMBER(tmu_tct1_w); + DECLARE_READ8_MEMBER(tmu_tst2_r); + DECLARE_WRITE8_MEMBER(tmu_tct2_w); + DECLARE_WRITE8_MEMBER(tmu_tmd_w); + + void install_peripheral_io(); + const address_space_config m_io_space_config; + const address_space_config *memory_space_config(address_spacenum spacenum) const { switch (spacenum) @@ -40,6 +60,11 @@ public: default: return nec_common_device::memory_space_config(spacenum); } } + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); }; diff --git a/src/mame/audio/hng64.c b/src/mame/audio/hng64.c index a79b1a46891..6c8c04ca026 100644 --- a/src/mame/audio/hng64.c +++ b/src/mame/audio/hng64.c @@ -12,7 +12,11 @@ sams64_2 (#)SNK R&D Center (R) HYPER NEOGEO64 Sound Driver Ver 1.14. (#)Copyrig fatfurwa (#)SNK R&D Center (R) HYPER NEOGEO64 Sound Driver Ver 1.14. (#)Copyright (C) SNK Corp. 1997,1998 All rights reserved buriki (#)SNK R&D Center (R) HYPER NEOGEO64 Sound Driver Ver 1.15. (#)Copyright (C) SNK Corp. 1997,1998 All rights reserved -the earlier revisions appear to have 2 banks of code (there are vectors at the end of the 0x1e0000 block and the 0x1f0000 block) +The earlier revisions appear to have 2 banks of code (there are vectors at the end of the 0x1e0000 block and the 0x1f0000 block) + +Those first two revisions also spam the entire range of I/O ports with values several times on startup causing some unexpected +writes to the V53 internal registers. The important ones are reinitialized after this however, I'm guessing this is harmless +on real hardware, as the code flow seems to be correct. data structures look very similar between all of them |